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LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 1 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 general description the LX1752 is a dual output synchronous buck controller using voltage mode pwm architecture. the single input voltage supply feature simplifies the design and offers a wide range of operation from 4.5 to 22 volts. each pwm has a soft-start pin for programming the output sequencing and serves as the shutdown control. current limit threshold is set with a single external resistor and protects the high-side and low-side mosfets by sensing the voltage drop generated from r dson . each pwm channel has its own external feedback compensation for performance optimization. internal gate drive circuitry provides 5v for the external upper and lower n channel mosfets. output voltages as low as 700mv, load currents up to 15a per phase and efficiency of 93% can be achieved with the flexible controller. operating alone or with other LX1752?s on a bus, three multi-phase interleaving options are available: two pwm channels with 180 separation; three pwm channels at 120 or four pwm channels at 90. this phasing is set by the tri-state input pin pset. this architecture minimizes the input capacitor requirements. the entire power supply design occupies a small footprint with the LX1752?s low profile 28 pin, mlp package of 4x5x1mm (jedec mo-220). important: for the most current data, consult microsemi ?s website: http://www.microsemi.com key features ? dual pwm controller, synchronous operation ? voltage mode pwm with external compensation ? single input supply, wide range 4.5v to 22v ? precision reference ? outputs as low as 700mv ? selectable pwm frequency up to 1.5mhz ? synchronization pin for pwm frequency ? independent and programmable soft start/enable for power sequencing ? integrated high current mosfet drivers ? programmable current limit ? lossless current sensing for current limit and short circuit protection ? pb-free, rohs compliant applications ? multi-output power supplies ? video card power supplies ? pc peripherals ? set top boxes ? point of load dc-dc converters product highlight vout vin 4.5v to 22v one of 2 pwm sections shdn sync part hox csx vcx hrx lox vin eax- ssenx vccl pgx agnd shdnx sync LX1752 eaox pset vsx rfreq package order info lq plastic mlpq 28 pin t a ( c) rohs compliant / pb-free 0 to 85 LX1752clq note: available in tape & reel. append the letters ?tr? to the part number. (i.e. LX1752clq-tr)
LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 2 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 absolute maximum ratings supply input voltage(v in) .............................................................. -0.3v to 22v supply voltage (vccl) .................................................................. -0.3v to 6.0v topside driver supply input voltage (vc x ) .................................... -0.3v to 28v topside current sense inpu t (vsx) .................................................. -0.3v to 28v current sense input (cs x ) .................................. -0.3v(-2.0v for 50ns), to 28v topside driver return input voltage (vhr x ).... -0.3v(-2.0v for 50ns), to 28v error amplifier inputs (eax-) ........................................................ -0.3v to 5.5v logic inputs (sync, pset, shdnx) .............................................-0.3 to vccl differential voltage: v hox -v hrx (high side return )......................... -0.3v to 6v soft start input ( ssenx)..................................................................-0.3v to v ref maximum ldo output cu rrent (vccl) ...................................................100ma maximum operating junc tion temperat ure ................................................ 150 c operating temperature ....................................................................-20 c to 85 c storage temperat ure range...........................................................-65 c to 150 c peak package solder reflow temp (40 seconds max exposure).... 260 c (+0, -5) note: exceeding these ratings could cause damage to the device. all voltages are with respect to ground. currents are positive into, negative out of specified terminal . x denotes respective pin designator (1 or 2). thermal data lq plastic mlpq 28-pin thermal resistance - junction to a mbient , ja 27 c/w junction temperature calculation: t j = t a + (p d x ja ). the ja numbers are guidelines for the thermal performan ce of the device/pc-board system. all of the above assume no ambient airflow. package pin out gnd sync shdn2 ssen2 ea2- eo2 vin cs2 vs2 vc2 h02 hr2 vccl l02 pgnd l01 hr1 h01 vc1 vs1 cs1 shdn1 vref pset rfreq ssen1 ea1- e01 1 2 3 4 5 6 7 8 9 1011121314 15 16 17 18 19 20 21 22 23 24 25 26 27 28 lq p ackage (top view) msc 1752 xxxx lq p ackage m arkings ?xxxx? denote date code and lot identification rohs / pb-free 100% matte tin pin finish functional pin description name pin description gnd 1 analog ground. connect this pin to a local analog ground plane. all low level signals are referenced to this ground and should return to this pin. sync 2 sync control line used on the multi-channel bus. wi re or?d negative going pulse with a common pull-up resistor. shdn x 3, 22 the shutdown pin is an i/o pin which connects to an internal open drai n transistor and an external pull up resistor. during a fault, this pin will be low during the discharge portion of hiccup mode, and high during the recovery (soft start) portion of hiccup mode.. used pr imarily for test purposes. may be used as a system level fault monitor. each shdn pin requires a pull-up resistor of 500 ? to 4.7k tied to vccl. ssen x 4, 25 soft start enable input. connect a capacitor from ssenx to gnd to set the soft-start time, the rise time of the output voltage during start up. if grounded the pwm is disabled. ea x - 5, 24 error amplifier inverting in put for the corresponding pwm channel denoted by ?x?. connect to the output via external network to regulate the output voltage. eo x 6, 23 error amplifier output ? connect to external loop compensation network for the corresponding pwm channel denoted by ?x? to provide an error signal to t he internal pwm comparator for duty cycle control. vin 7 controller supply voltage. this is the input to the internal 5v ldo.
LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 3 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 functional pin description cs x 8, 21 over-current limit set ? connecting a resistor between cs x pin and the junction of the drain of the low-side nmosfet and the source of the high-side mosfet sets the current limit threshold for the corresponding pwm channel denoted by ?x?. a minimum of 200 ohms must be in series with this input. whenever the current limit threshold is reached for 4 consecutive cl ock cycles the shutdown latch is set and the soft start capacitor is discharged through an internal resistor initiating shutdown and t hen a soft start to generate a hiccup mode current limit. vs x 9, 20 voltage reference for high side current sense. ?x? denotes corresponding phase. connect this pin directly to the high-side mosfet?s drain. vc x 10, 19 pwm channel high-side mosfet gate driver supply. connect to the flying capacitor bootstrap supply to ensure proper high-side gate driv er supply voltage. ?x? denotes the corresponding pwm channel. ho x 11, 18 high side mosfet gate driver ? ?x? denotes corresponding pwm channel. hr x 12, 17 high side driver return, connect this pin to the high side mosfet source. ?x? denotes the corresponding pwm channel. vccl 13 output of the +5v ldo regulator. supplies the inte rnal circuit and the external mosfets gate drivers. for 4.5v < vin < 5.5v, this pin is conn ected externally to vin. for vin > 6v this pin supplies +5v to the internal circuit and the external mosfets gate drivers connect a minimum of 4.7f ceramic capacitor from this pin to gnd. lo x 14, 16 low side mosfet gate driver ? ?x? denotes corresponding pwm channel. pgnd 15 power ground pin for the low-side mosfet drivers. connect low-side mosfets? source directly to this pin, which connects to power ground plane rfreq 26 the resistor value from this pin to gnd sets the pwm frequency. pset 27 a tri-state logic level input that se lects the phase position of the two pwm channels from the sync pulse. a logic low, gnd, will set the pwm phases at 0 and 180 degrees. an open pin, tri-state, will set the pwm phases at 90 and 270 degrees. a logic high, v ccl, will set the pwm phases at 120 and 240 degrees. vref 28 an internally generated voltage reference of 0.8v t hat is buffered and brought out on this pin. if used, connect a 470pf ceramic capacitor to gnd. note: x denotes the pwm channel: 1 or 2
LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 4 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 electrical characteristics unless otherwise specified, the following specificati ons apply over the operat ing ambient temperature 0 c t a 85 c except where otherwise noted and the following test conditions: v in = 12v, v cx = 17v, hox = 1000pf load to hrx, lox =1000pf load to gnd, v hrx = 12v, (f = 800khz). LX1752 parameter symbol test conditions min typ max units ` ic electrical characteristics vin 6.0 22 connect vccl to vin externally 4.5 5.5 input voltage v operation current i vin no switching 6 ma feedback voltage eax- initial accuracy; t a = 25c 0.691 0.700 0.709 v 4.5v vin 22v 0.689 0.711 high side minimum pulse width (note 3, note 5) pw min switching frequency = 800khz to1.5mhz measured between 1.5v rise to 1.5v fall of hox ? hrx. 80 ns maximum duty cycle pwm dc measured between hox-hrx 1.5v rise to hox- hrx 1.5v fall. 88 92 % buffered reference voltage v ref 0ma i vref 1.0ma 0.784 0.800 0.816 v ` error amplifier dc open loop gain, 70 db unity gain bandwidth (note 2) av ugbw 10 mhz high output voltage v oh i source = 2ma 3.5 v low output voltage v ol i sink = 100a 100 mv input common mode range 0.2 1.0 v input bias current i in 30 na ` current sense cs bias current (source) i set v csx to v hrx = 0.2v; v pgnd = 0v, vcx to vhrx = 5.0v 44 50 57 a cs trip threshold offset v trip referenced to v csx , v pgnd = 0v -20 0 20 mv cs delay (blanking) t csd (note 5) 150 ns ` output drivers ? n channel mosfets drive rise and fall time t r/f c l = 1000pf 40 ns dead time ? high side to low side or low side to high side t dead measured between 1.5v crossings of hox-hrx and lox. 40 ns high side driver rds on drive high i hox = 100ma (note 5) 4.8 drive low ho x _rds on i hox = -100ma 3.3 ohm low side driver rds on drive high i lox = 100ma 4.4 drive low lo x _rds on i lox = -100ma 3.3 ohm ` sync-frequency generator maximum clock frequency f max r freq = 19.1k ? 1.4 1.5 1.6 mhz minimum clock frequency f min r freq = 178k ? 180 200 220 khz ramp amplitude v ramp 1.2 vpp frequency stability 4.5v vin 22v 5 %
LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 5 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 electrical characteristics (continued) unless otherwise specified, the following specificati ons apply over the operat ing ambient temperature 0 c t a 85 c except where otherwise noted and the following test conditions: v in = 12v, v cx = 17v, hox = 1000pf load to hrx, lox =1000pf load to gnd, v hrx = 12v, (f = 800khz). LX1752 parameter symbol test conditions min typ max units ` uvlo and soft-start (ss) start-up threshold (vccl) vccl rising 3.75 4.35 v hysteresis (note 2) 0.2 0.30 v ss input resistance r ss 20 k ? ss shutdown threshold v shdn 85 130 mv soft start time c ss = 0.1uf; v out rise time from 0v to 90% of output voltage set by feedback (note 2) 4.30 ms hiccup mode duty cycle c ss = 0.1f; 100% * on time/off time + on time 4 % ` internal ldo regulator regulated output vccl internal + external load: 0ma < i vccl < 100ma; 6v < vin<22v. 4.5 5.5 v ` pset tri-state input logic level low threshold pset percentage of vccl (note 4) 22 % logic level open threshold percentage of vccl (note 4) 40 50 60 % logic level high threshold perc entage of vccl (note 4) 84 % ` logic input / output ? open drain external pull up resistor threshold logic low external pull-up resistance = 500 ohms to vccl 1.0 1.5 v sync bus sync input pulse width measured at 50% of vccl; fall time < 5ns, rise time < 20ns 30 100 ns shutdown shdn threshold logic low; falling edge 0.8 1.5 v ` switching regulators phase to phase position pset = vccl; measured ho1 to ho2 80 102 120 degrees pset = open; measured ho1 to ho2 140 165 190 degrees pset = gnd; measured ho1 to ho2 160 180 210 degrees ` thermal shutdown die temperature tsd rising temperature; hiccup mode operation at limit 165 c die temperature hysteresis tsd rising temperature; hiccup mode operation at limit 10 c
LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 6 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 system characteristics unless otherwise specified, the following specificati ons apply over the operat ing ambient temperature 0 c t a 85 c except where otherwise noted and the following test conditions: v in = 12v; f = 800khz; tested using the applic ation circuit referenced in figure 2. LX1752 parameter symbol test conditions min typ max units ` switching regulators system characteristics line regulation vin = 6v to 22v 0.5 0.5 % load regulation 0 to 5 amps output load -0.2 0.2 % note 1: x denotes the pwm channel: 1 or 2. note 2: assured by design and characterization. not ate tested. note 3: for switching frequencies less than 800khz, mi nimum pulse width is defined by the formula pw min = 0.064 x 1/fsw note 4: pset logic threshold specif ications are dependent on vccl voltage level. the following formulas apply: pset logic high min. threshold = 0.81 x vccl + 0.140 (rising) pset logic low max. threshold = 0.19 x vccl + 0.028 (rising) note 5: guaranteed by design. not ate tested.
LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 7 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 typical characteristics @ 25c (refer to figure 2) LX1752 line regulation - 1 amp load -0.5% -0.4% -0.3% -0.2% -0.1% 0.0% 0.1% 0.2% 0.3% 0.4% 0.5% 5 10152025 input voltage (v) % voltage change vout1 vout2 line regulation line regulation - vccl i vccl = 20ma -1.0% -0.8% -0.6% -0.4% -0.2% 0.0% 0.2% 0.4% 0.6% 0.8% 1.0% 5 10152025 input voltage (v) % voltage change % change vccl line regulation LX1752 load regulation @ vin = 12v -0.5% -0.4% -0.3% -0.2% -0.1% 0.0% 0.1% 0.2% 0.3% 0.4% 0.5% 0123456 output current % voltage change % change v1 % change v2 load regulation LX1752 efficiency vs. output current 800khz; vin = 12v; vout1 = 5.0v; vout2 = 3.3v 0.0% 10.0% 20.0% 30.0% 40.0% 50.0% 60.0% 70.0% 80.0% 90.0% 100.0% 0123456 output current efficiency vout1 vout2 efficiency vs. output current
LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 8 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 typical characteristics @ 25c (refer to figure 2) output load step response short circuit current limit during hiccup mode output load release response overcurrent protection limit - i limit set for 6.5a vout1 load current vout1 load current vout2 pwm inductor current vout2 pwm inductor current
LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 9 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 typical characteristics @ 25c (refer to figure 2) fault hiccup mode ? vout2 shorted soft start at power-up dual 1752s synchronized and interleaved at 90 intervals zoom in soft start at power-up vout1 pwm vout2 pwm ss1 ss2 unit#1 vout1 pwm unit#2 vout1 pwm unit#1 vout2 pwm unit#2 vout2 pwm vout2 vout2 pwm inductor current eo2 vout2 pwm eo2 inductor current vout2
LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 10 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 simplified block diagram cs comp + - amplifier/ compensation + - error comp + - v ref hiccup +5v regulator lx esr c out c in +5v out x r set vccl lox hox vcx csx ea-x agnd pwm i set eaox vin pgx ssx tsd f r s +5v css 500k hrx bg vref q r s 50ua + + 20k + - 100mv fault ssmsk clkx 4 cycle counter ss comp uvlo vin vin shdnx vsx rampx 4.7k cs comp + - sync rfreq cfreq 500 high & low limit detector +5v freq ramp i ramp pset vccl tri - state input pset mux clk1 clk2 ramp2 ramp1 pset pwm1 pwm2 high tri low 120 240 90 270 0180 phase shift from sync sync buss figure 1 ? simplified block diagram
LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 11 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 application circuit 10uf 0.1uf 1/2 irf8910 3.40k 1% 40.2k 1% 0.1uf 160k cmdsh-3 1.0uf u1 LX1752 gnd 1 sync 2 shdn2 3 ssen2 4 ea2- 5 eo2 6 vin 7 cs2 8 vs2 9 vc2 10 ho2 11 hr2 12 vccl 13 lo2 14 vref 28 pset 27 rfreq 26 ssen1 25 ea1- 24 eo1 23 shdn1 22 cs1 21 vs1 20 vc1 19 ho1 18 hr1 17 lo1 16 pgnd 15 1/2 irf8910 0.22uf 1k 1/2 irf8910 10uf 4.7uf 6.3v 10uf 820uf 6.3v + 1.2nf 5.62k 1% 21.0k 1% 1/2 irf8910 160k 21.0k 1% cmdsh-3 4.7k 3.3uh 1uf 3.3uh 0.1uf 1.2nf 10uf 820uf 6.3v + 2.32k 2.32k +5v ldo +12v +12v +12v +5v ldo 3 4 5 6 1 7 8 2 2 7 8 1 3 5 6 4 vout1 rtn vout2 rtn 3.3v @ 5 amps 5.0v @ 5 amps to additional LX1752's 4.7k figure 2 ? LX1752 application schematic
LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 12 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 theory of operation d etail d escription the LX1752 is an independent dual-output, voltage-mode, synchronous buck controller integrated circuit. output current sensing is through rds on measurement of the external power mosfets, and is set by a single user- programmable resistor for each output. the internal pwm clock frequency is user programmable from 200khz to 1.5mhz, via a single programming resistor. synchronizing of the internal pwm clock is possible for multiple LX1752 ics using either an internally generated sync pulse, or a sync signal from an external source. synchronized LX1752 ic?s pwm outputs can be phase positioned relative to each other via a single pin configuration, allowing 90, 120, or 180 phase separation between outputs. each of the two LX1752 outputs has external feedback compensation, for flexibility of output filter component selection. o scillator f requency the LX1752 ic?s internal pwm oscillator is user- programmable from 200khz to 1.5mhz. programming is provided by a single resistor, r freq , connected between the rfreq and gnd pins. the value of this resistor is based on the following formula: 156 5 56 27 1 9 . f e . ) k ( r osc freq ? = ? e xternal c lock s ynchronization the LX1752 provides external clock synchronization of the pwm clock, for multiple LX1752 ics. this feature is implemented via a common buss connected to the LX1752 ic?s sync pin. the sync pin is an i/o pin, with an open drain switch to ground providing the internally-generated output sync pulse. this allows each LX1752 sync pin to connect to a common buss in a wi red-or configuration. for proper operation, a pull-up resistor between the LX1752 ic?s vccl and sync pins must be provided. the total parallel pull-up resistance must be great er than 500 ohms for all ics connected to the common buss. the total pull-up resistance on the sync pins is sized such that the sync pulse rise time is (at maximum) less than ? the pwm clock period. under synchronized operation, each LX1752 is synchronized to the falling edge of the sync pulse. multiple LX1752 ics will synchronize to the controller with the highest pwm clock frequency. for proper operation, it is advised to set one controller?s pwm frequency 15% higher than the others to insure it will always provide the master clock frequency. an externally generated clock pulse may be used to synchronize multiple LX1752 ics. the LX1752 synchronizes to an external signal by resetting the pwm ramp on the falling edge of the si gnal input at the sync pin. when using an external clock for synchronizing, the external clock should be provided through an open drain or open collector connection, with an external pull-up resistor between the sync and vccl pins. . for proper operation, the external clock frequency must be at least 15% higher than the LX1752 internal pwm frequency set by r freq , and external clock widths should be less than ? the nominal period set by r freq . figure 3 and 4 are an example of an external sync circuit and the resultant waveforms at the moment of sync clock capture. 10k 1k 2n7002 vccl (LX1752 pin 13) to LX1752 sync pin (pin 2) external sync clock figure 3. external sync circuit figure 4. LX1752 external sync waveforms LX1752 hr1 pin external sync clock LX1752 sync pin
LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 13 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 theory of operation o utput p hase p ositioning the LX1752 offers phase positioning of the output pwms. using two synchronized LX1752 controllers, up to four pwm outputs may be interleaved at 90 intervals or 3 pwm outputs at 120 intervals. output phase positioning relative to the sync pin signal can be configured via the LX1752?s pset pin. the pset pin is a tri-mode input pin, whose state determines the pwm output?s phase relationship. pset pin settings pset connection pwm 1 position (relative to sync pin signal) pwm 2 position (relative to sync pin signal) vccl 120 240 open 90 270 gnd 0 180 o ver -c urrent p rotection and h iccup m ode the LX1752 senses the r ds(on) of both the upper (control) and the lower (synchronous) mosfet for current limit detection. rds on sensing is done via three pins: cs x , vs x , and pgnd. the upper (control) fet rds on is sensed via the cs x and vs x pins. the lower (synchronous) fet rds on is sensed via the cs x and pgnd pins. current limit is set by the resistor on the cs x pin, and is based on the following calculation: (min) i (max) rds i r cs on lim cs = where i cs (min) = minimum cs pin programming current the upper and lower mosfet current sense contain an internal blanking circuit which delays current sensing for 150ns after their respective mosfet is switched on. this reduces possible false current lim it detection due to ringing. r cs values should be chosen such that delays created by the cs x resistor and any pcb capacitance on the cs x pin are less than 100ns; this is to insure the cs x pin voltage rises faster than the current sense blanking time. for best operation of the lx1 752 current sense circuit, the vs x pin and cs x resistor must be kelv in-connected to their respective output mosfet drain and source pins. when an over current limit is detected, a signal to reset the pwm latch is generated, and the output pwm is truncated on a cycle by cycle basis. after 4 continuous pwm cycles of current limit detection, hiccup mode is started. at the initial start of hiccup mode, the ho x output mosfet for that phase is held off, and the soft-start capacitor (c ss ) is discharged at a rate 1/25 of the soft-start rate. when the ss pin voltage decreases to the 0.1v pwm enable threshold, the hiccup mode cycle ?off time? finishes, the output pwm is switched on, and the circuit soft-starts again. duri ng the soft start period, hiccup mode is disabled, however, cy cle by cycle current limit is functional, insuring output current is kept at the current limit setting. once ssen x reaches 720 mv (90% of the 800mv ssen x pin reference voltage), if an over current condition still exists, hiccup mode will again be initiated, the ss capacitor will discharge, and the pwm output will be switched off until the ss voltage decreases to 0.1v. the low duty cycle of hiccup mode, in combination with cycle by cycle current limiting, reduces the power dissipation of the output mosfets during a fault condition, thus providing a very reliable and robust overload and short circuit protection i nternal ldo r egulator the LX1752 contains a +5v ldo regulator for providing power to internal circuits, external flying bootstrap capacitors, mosfet gate drives, and pull-up resistors for the sync and shdn pins. the +5v ldo output is available at the vccl pin. for proper operation, a minimum 4.7uf capacitor is required between the vccl and gnd pins. total continuous ldo current should be limited to 100ma. u nder v oltage l ockout (uvlo) at power up, the LX1752 monito rs the internal ldo voltage at the vccl pin. the vin supply voltage has to be sufficient to produce a volta ge greater than the uvlo threshold at the vccl pin before the controller will come out of the under-voltage lock-out state. at vccl voltages below the uvlo threshold, both soft-start (ss) pins are held low, the internal pwm oscillator is disabled, and all mosfets are held off. s oft -s tart once the vccl output is ab ove the uvlo threshold, a capacitor connected between the ss x and gnd pins begins charging by a 20k internal resistor connected to an 800mv reference. the capacitor voltage at the ss pin rises as a simple rc circuit. the voltage at the ss pin controls its respective output voltage through the error amplifier?s non- inverting input. the output voltage will follow the ss pin voltage if sufficient charging current is provided to the output capacitor. due to the exponential rise of the ssx pin voltage, the fastest output voltage rate of rise occurs during the first time constant of the ssx capacitor, and the internal 20k ? resistor. during this period, the feedback reference voltage will reach 63% of its nominal setting. this rate of rise can be
LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 14 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 theory of operation used to calculate the average startup current seen by the inductor: load ss out out startup i c e v . c i + = 3 20 63 for lowest in-rush currents, soft start capacitors should be sized such that the output voltage rise is slower than the input voltage (vin) rise during power-up. e xternal p wm e nable the LX1752?s pwm outputs can be disabled externally by holding the ss x pin below 0.1v with an open drain transistor connected to ground. at ss x pin 0.1v, both output mosfets are held off. using this method, pwm enable and soft start can be controlled through an external signal. this method is useful for controlled power-up sequencing. b uffered vref o utput the LX1752 provides a buffered output of the internal 800mv reference. this output may be used as a reference for an external ldo or any a pplication where an 800mv reference is required. current is limited to a maximum of 1ma from this output. e xternal f eedback and c ompensation c omponents the LX1752 has pin access to each output?s respective error amplifier inverting and output signals. this topology offers full freedom for output filter component selection and control loop optimization for stable high bandwidth operation. see compensation section below.
LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 15 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 application information o utput i nductor s election the output inductor value is selected based on the desired ripple current. inductor ripple current should be in the range of 20% to 40% of the maximum output current. higher inductance values result in lower peak to peak ripple current, at the expense of slower transient response. lower inductor values provide a higher current slew rate in response to a step change in load current, howeve r peak to peak ripple current increases, requiring an output filter capacitor with a smaller esr specification to meet output ripple voltage requirements. the inductor value can be calculated by: sw ripple out in f d i v v l ? = where d = operating duty cycle f sw = pwm switching frequency i ripple = desired peak to peak ripple current o utput c apacitor s election the key selection parameters for the output capacitor are the actual capacitance value, the equivalent series resistance (esr), the equivalent series inductance (esl), and the voltage rating requirements, which affect overall stability, output ripple voltage, and step load transient response. the output ripple has three components: variation in the charge stored in the output ca pacitor, the voltage drop across the esr, and the voltage drop ac ross the esl, caused by the current into and out of the capacitor. the following equations estimate the wors t-case output ripple voltage: ) esl ( ripple ) c ( ripple ) esr ( ripple ripple v v v v + + = where: esr i v ripple ) esr ( ripple = sw ripple ) c ( ripple f c i v = 8 esl l esl v v in ) esl ( ripple + = high output current may require paralleling multiple capacitors to meet output rippl e requirement, as it reduces esr and esl, which are the major contributors to output ripple voltage. for step load conditions, capacitor esr will be the dominant factor determining the size of the initial output voltage excursion. capacitor esr should be selected such that: transient ripple v ) i i ( esr < + where i ripple = peak to peak inductor ripple current i is the maximum load current step change v transient is the maximum allowed output voltage excursion during a load step change a second consideration when determining the output capacitor is the minimum capacitance value required to limit voltage overshoot during a large load release, such as a transient from full load to no load. in this case, the output capacitor must be large enough to absorb the excess energy present in the inductor. minimum output capacitance is based on the desired maximum overshoot and output inductor value, and is calculated by the following formula: () 2 2 2 out overshoot out tran min v v v l ) i ( c ? + = where i tran = specified maximum load transient (full load to no load) l = output inductor value v overshoot = maximum allowable voltage overshoot i nput c apacitor s election rms ripple current is the primar y factor when selecting the input capacitor. input rms ripple current is based on operating duty cycle (d), and is at a maximum at d = 50%. the following formula is used for calculating the input rms current for each output: in out in out ) max ( out inrms v ) v v ( v i i ? =
LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 16 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 application information input capacitance is largely dependent on the source impedance of the power source; however, for most cases the general rule of thumb is to use a total minimum capacitance of 10uf for every ampere of input ripple current. this is best achieved through a combination of ceramic capacitors placed as close to the output fets as possible, and an electrolytic capacitor placed in close proxi mity to the LX1752 and it?s associated circuit components. f eedback and c ompensation c omponent s election the LX1752 is a voltage mode controller that uses external feedback components to establish output dc voltage and closed-loop bandwidth. this control scheme consists of an error amplifier, whose output controls a pwm modulator, which in turn drives an lc filter to produce the dc output (see figure 5). a simple way to analyze the closed loop system is to break the loop and separate the elements into two sections: first, the combined pwm modulator and output lc filter, called the control to output section, and second, the error amplifier section (see figure 6). once separated, the total gain through the two sections is analyzed. pwm modulator output lc filter error amplifier supply rail input (v in ) output voltage (v out ) figure 5. voltage mode control scheme pwm modulator output lc filter error amplifier supply rail input (v in ) loop gain (must = 1 at crossover frequency) control to output section figure 6. separating the loop components to achieve a proper closed lo op system, first the crossover frequency is determined, after which the control to output section is analyzed for it?s gain and rolloff response at that frequency. once the response at the crossover frequency is known, the error amplifier compensation components are chosen such that the overall gain of the two sections is equal to 1 (or 0db) at the crossover frequency: 1 = = eaxo cto fc g g g where g fc = loop gain at crossover frequency g cto = control to output section gain at crossover frequency g eaxo = error amplifier section gain at crossover frequency the lc filter creates a complex pole (-2 slope) in the control to output section?s response, along with a zero created by the output capacitor es r. so, in addition to the gain of 1 at the crossover frequency, the phase response of the error amplifier section must be designed such that the response of the control to output section is compensated to achieve a first order response (-1 slope) at the crossover frequency (see figure 7). this will insure that the phase margin at the crossover frequency is greater than 45. this is accomplished by designing the er ror amplifier?s response to counteract the pole and zero created by the output lc filter. -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 10 100 1000 10000 100000 frequency (hz) gain (db) l-c corner frequency esr-c corner frequency -2 slope -1 slope figure 7. output filter gain vs. frequency
LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 17 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 application information when selecting feedback and compensation components, the following steps are required: 1) determine the input resistor value. 2) determine the output voltage setting resistor. 3) determine the control-to-output gain at the desired crossover frequency. 4) determine the error amplifier gain at the desired crossover frequency. 5) decide if type two or type three compensation is used 6) calculate the feedback components for the desired compensation type. 1. d etermine the input resistor value : the input resistor is sized based on the error amplifier input bias current specification. high bias currents can create output voltage errors in large-value input resistors due to the ir drop created by this current. the LX1752 has a specified input bias current of 30na (max.). this will generate a 30uv (max.) output voltage error for every 1k ? of input resistance. this error is small enough to neglect in most cases. for this example, use 21k ? (see figure 8). 2. d etermine the output voltage setting resistor : the voltage setting resistor is the resistor connected between the error amplifier?s inverting input and ground. this resistor, in conjunction with the input resistor, forms a dc voltage divider that determines the output voltage level (see figure 8). because the voltage divider is connected to the input of the error amplifier, the control loop will force the dc output voltage such that the voltage developed across the setting resistor will equal the feedback voltage reference, v fb . v fb for the LX1752 is specifi ed at a nominal 0.7v at room temperature. the following equation determines the voltage setting resistor: (equation 1) 7 0 7 0 . v . r r out input set ? = for our example, if r input = 21k ? , and desired v out = 5v, then r set = 3.42k ? . regulator output error r input + _ erramp r set + vref 0.7 closed-loop output voltage will drive this node to 0.7v figure 8. output dc setting resistors 3. d etermine the control to output gain at the desired crossover frequency : the first step in determining the control to output gain is to decide on the closed-loop bandwidth, or crossover frequency of the system. bandwidths that are too wide (high crossover frequency) can amplify switching noise. bandwidths that are too low will have poor transient response times. the general rule-of-thumb is that the crossover frequency (f c ) should be no greater than 1/5 th the switching frequency, or : (equation 2) 5 sw c f f the error amplifier gain will limit the maximum crossover frequency. the total bandwidth capable will be based on the output filter components, the dc input voltage, and the error amplifier gain. a good rule of thumb would be to limit the bandwidth to 100khz or less. once the crossover frequency has been determined, the next step is to determine the total input to output gain of the control to output section at the crossover frequency. the input to output gain expression for the control to output section is:
LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 18 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 application information (equation 3) lc pwm in cto g g v g = where v in = dc input voltage to the output mosfets g pwm = pwm modulator gain g lc = output lc filter gain the pwm modulator gain is based on the peak to peak pwm ramp voltage, and is simply: (equation 4) ramp pwm v g 1 = where v ramp = the peak to peak ramp amplitude the LX1752 has a nominal ramp amplitude = 1.2v the output lc filter creates two frequency corners in the output response: first, a complex pole with -2 slope (40db/decade) rolloff and 180 phase shift is created at the lc resonance frequency. second, a zero, is created at the output capacitor and its respective equivalent series resistance (esr) corner frequency. these two frequency corners are found by the following equations: (equation 5) lc f p = 2 1 and (equation 6) ) rc ( f z = 2 1 where l = output filter inductor c = output filter capacitor r = output filter capacitor esr at the crossover frequency, the lc filter?s response can be found using the calculated pole and zero. this method of calculating the response will depend on the relationship of the output capacitor-esr zero corner frequency to the chosen crossover frequency: (equation 7) c z c z p lc f f ; ) f f ( f g = 2 or (equation 8) c z c p lc f f ; f f g > ? ? ? ? ? ? ? ? = 2 example calculations: using the application circuit: v in = 12v l = 3.3uh c= 820uf esr = 21m ? ramp amplitude = 1.2v crossover frequency = 80khz using equations 5 and 6, find the pole and zero frequency corners: khz . e e . f p 06 3 820 3 3 2 1 6 6 = = ? ? khz . e e f z 25 9 820 21 2 1 6 3 = = ? ? the esr-capacitor zero frequency of our example is less than the crossover frequency. use equation 7 to determine the lc filter gain at the crossover frequency: 3 2 65 12 80 25 9 06 3 ? = = e . khz khz . khz . g lc the pwm modulator gain is found using equation 4: 3 833 2 1 1 ? = = e . g pwm using equation 3, the total control to output section gain at the crossover can be determined: 3 3 3 45 126 65 12 833 12 ? ? ? = = e . e . e g cto 4. d etermine the e rror a mplifier gain at the desired crossover frequency : our example control to output section gain is 0.12645 at the crossover frequency. the error amplifier gain required for unity gain at the crossover frequency will be:
LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 19 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 application information (equation 9) 908 7 45 126 1 1 3 . e . g g cto eaxo = = = ? once the required error amplifier gain is determined, the error amplifier open loop gain should be examined to assure the error amplifier has enough open-loop gain at the crossover frequency to satisfy the above gain requirement: (equation 10) 1 2 2 + ? ? ? ? ? ? ? ? ? ? eaol c eaol eaol eaxo f f g g g where g eaol = error amplifier open loop gain f eaol = error amplifier open loop bandwidth using the LX1752 error amplifier as an example: g eaol = 70db, gain magnitude = 3162 f eaol = 10mhz 24 120 1 10 2 80 2 3162 3162 . mhz khz = + ? ? ? ? ? ? the above equation shows there is ample error amplifier open-loop gain available at the crossover frequency. 5. d ecide if t ype t wo or t ype t hree c ompensation is used . at this point, the compensation type can be decided. the two standard methods for compensating a voltage mode buck converter are type two and type three compensation (the name references the number of compensating slopes in the response; type two has two, type three has three). see figures 9 & 10. both type two and type three compensation are identical in that they are designed to offset the complex pole and esr zero of the output lc filter. where they differ is in the number of compensating poles and zeros provided. type two compensation is known as a ?single pole-zero? compensation, in that it supplies a single compensating zero, and a single compensating pole in the error amplifier?s response. the type three compensation is known as ?pole-zero pair? compensation, in that it supplies two compensating poles and two compensating zeros. the deciding factor for which of the two methods of compensating the loop can be used is based on the amount of available phase margin present in the control to output section at the crossover frequency. because type two compensation does not provide an extra phase boost after the complex lc pole, the phase boost provided by the output capacitor ? esr combination is critical when using type two compensation. therefore, the relationship of the complex lc pole, f p , to the esr-capacitor zero, f z,. becomes important: if fz/fp is 5 or less, then type two compensation may be used. type three compensation should be used otherwise. regulator output error r1 c1 r2 + _ c3 erramp r3 c2 r4 + vref 0.7 figure 9. type 3 compensation regulator output error r1 c1 r2 + _ c2 erramp r3 + vref 0.7 figure 10. type 2 compensation
LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 20 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 application information t ype t hree c ompensation c omponent s election . type three compensation contains 2 poles and 2 zeros in the feedback loop to counterac t the complex pole created by the l-c output filter, and the zero created by the esr - output capacitor. type 3 compensation should be used when the desired crossover frequency is lower than the esr zero frequency, or when it is higher than the esr zero frequency and the esr zero frequency is higher than 4 to 5 times the output lc filter corner frequency. typical feedback response is shown in figure 11. 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 10000 100000 1000000 frequency (hz) gain (db) fz1 fz2 fp1 fp2 g fb 1 g fb 2 crossover frequency (f c ) figure 11. typical type 3 feedback response to calculate the values, first the two compensation zeros and two compensation poles must be set. the two compensation zeros are set to counteract the complex l-c pole at two locations, both multiples of the complex l-c pole: 1. set the first compensation zero frequency (fz1) to the l-c pole/4: (equation 11) 4 f 1 f p z = 2. set the second compensation zero frequency (f z 2) equal to the l-c pole frequency: (equation 12) p z f 2 f = 3. next, the first compensation pole (f p 1) is set equal to the esr - capacitor zero frequency: (equation 13) z p f 1 f = 4. finally, the last compensation pole (f p 2) is set equal to 1/2 the switching frequency: (equation 14) 2 f 2 f sw p = in order for the feedback response to be correct, the feedback loop must be set to two gain levels, g fb 1, and g fb 2 g fb 2 is the highest gain value of the two levels, and is the gain required to boost the control to output gain to 1 at the crossover frequency. g fb 2 is established after the first compensation pole frequency (f p 1), and is the complement of the total control to output gain (g cto ) at the selected crossover frequency: (equation 15) cto fb g 1 2 g = g fb 1 is the gain level established after the first compensation zero frequency (fz1). g fb 1 gain is derived from the crossover frequency gain (g fb 2). the method for calculating g fb 1 is dependent on whether the output capacitor ? esr zero corner frequency is greater or less than the crossover frequency. condition 1; f z f c (equation 16) ? ? ? ? ? ? ? ? = 1 f 2 f 2 g 1 g p z fb fb condition 2; f c f z this condition occurs when the capacitor-esr zero frequency corner is greater than the chosen cutoff frequency. this is a common condition with ceramic output capacitors. for this condition, g fb 1 is found by: (equation 17) ? ? ? ? ? ? ? ? = c z fb fb f 2 f 2 g 1 g to calculate the compensation component values (reference figure 9): first, select resistor r1. this topic is covered under ?determine the input resistor value? on page 17. resistor r4 may be selected at this time; however it is for setting the output dc level only, and is not used in the compensation calculations. r4 is covered under ?determine the output voltage setting resistor? on page 17.
LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 21 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 application information next, calculate the value of r2; r1 & r2 will set the gain for g fb 1: (equation 18) 1 g 1 r 2 r fb = calculate the value for c1; c1 & r2 set the first zero frequency: (equation 19) 2 r ) 1 f ( 2 1 1 c z = the next value is for r3; r3||r1 & r2 set the gain for g fb 2: (equation 20) () 2 r 2 g 1 r 2 r 1 r 3 r fb ? = calculate c2; c2 & r1 + r3 se t the second zero frequency: (equation 21) ) 3 r 1 r )( 2 f ( 2 1 2 c z + = finally, the value for c3 + c1 & r2 sets the second pole frequency: (equation 22) 1 ) 2 r 1 c ) 2 f ( 2 ( 1 c 3 c p ? ? ? = the first pole frequency, f p 1, will be correct with the values chosen. to verify: (equation 23) ) 2 c 3 r ( 2 1 1 f p = example calculations: assume the following design parameters and component values: ? v in = 3.4v ? v out = 1.24v ? v ramp = 1.2v ? pwm frequency = 800khz ? error amplifier gain = 3162 (70db) ? error amplifier bandwidth = 10mhz ? output inductor (l) = 2.2uh ? output capacitor (c) = 3000uf (2 x 1500uf capacitors in parallel) ? capacitor esr = 5.5m ? (2 capacitor esr values of 11m ? in parallel) ? crossover frequency = 80khz referencing figure 7: step 1 ? determine the input resistor (r1) value: keep the input resistor value as low as practical to reduce input bias errors. for this example, choose 10.7k ? 1% (1% part for dc output voltage accuracy). step 2 ? determine the dc output ?setting? resistor (r4): using equation 1, and the values chosen for r input and v out : r set (r4) = 13.6k ? . use 13.7k ? 1% (1% part for dc output voltage accuracy). step 3 ? determine the control to output section gain: using equation 5, and the values chosen for l and c: f p = 1.96khz using equation 6, and the values chosen for esr and c: f z = 9.65khz the esr ? capacitor zero frequency is less than the chosen crossover frequency. use equation 7 to calculate the gain of the lc filter section: g lc = 4.974e-3 using equation 4, pwm modulator gain is: g pwm = 0.833 finally, using equation 3 and the chosen vin value of 3.4v: g cto = 14.086e-3 step 4 - determine required error amplifier gain: using equation 9, the required error amplifier gain: g eaxo = 71 use equation 10 to determine the error amplifier open-loop gain at the crossover frequency: g eaxo 120.2 based on equation 10, there is enough gain available. step 5 ? determine type two or type three compensation: for this example, f z /f p is greater than 4. we will use type three compensation. step 6 ? select type three components (reference figure 9): using equations 11 through 14, determine the compensation frequency components: fz1 = 490hz
LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 22 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 application information fz2 = 1.96khz fp1 = 9.65khz fp2 = 400khz calculate the highest of the two feedback gains using equation 15: g fb 2 = 71 the esr ? capacitor zero frequency is less than the chosen crossover frequency. use equation 16 to calculate the lower of the two feedback gains: g fb 1 = 14.4 using equations 18 through 22, calculate the values for the compensation components: r2 = 154k ? ; use 150k ? 5% r3 = 2.72k ? ; use 2.7k ? 5% c1 = 2.11nf; use 2.2nf c2 = 6.05nf; use 5.6nf c3 = 2.6pf; too small; omit this capacitor. in this example, c3 value of 2.6pf is far too small to be of practical use. in this case it may be omitted without any consequence. if the additional roll off provided by c3 is still desired, the value of r input (r1) may be set lower, and the feedback components recalculate d. this will raise the value of c3. as an alternative, set f p 2 to a lower frequency, however do not set lower than 1.5 x the crossover frequency (f c ). figure 12 is the schematic of the example feedback compensation. regulator output error r1 c1 r2 + _ c3 erramp r3 c2 r4 + vref 0.7 not used 150k 5% 2.2n 10.7k 1% 5.6n 13.7k 1% 2.7k 5% figure 12. example circuit feedback and compensation figure 13 is the bode plot of the closed loop response of our example. 10 100 1 . 10 3 1 . 10 4 1 . 10 5 1 . 10 6 150 100 50 0 50 100 150 gain phase overall loop gain & phase frequency figure 13. bode plot of example circuit
LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 23 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 application information t ype t wo c ompensation c omponent s election . type two compensation contains a single zero and pole in the feedback loop to counteract the complex pole created by the l-c output filter. this type of compensation does not provide an extra phase boost after the complex lc pole frequency, which is provided by type 3 compensation. this type of compensation is used when the phase margin of the control to output section is greater than the minimum closed loop phase margin desired at the crossover frequency. typical frequency response is shown in figure 14. 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 10000 100000 1000000 frequency (hz) gain (db) fz1 fp1 g fb crossover frequency (f c ) figure 14. typical type 2 feedback response the component values for type 2 compensation are found using identical equations and methods as in type 3. the main differences are that type 2 has only one gain level, one compensating zero, and one comp ensating pole to calculate. as in type 3 compensation, establish the frequency corners: 1. set the first compensation zero frequency (fz1) to the l-c pole/4: (equation 24) 4 f 1 f p z = 2. set the compensation pole (f p 1) equal to 1/2 the switching frequency: (equation 25) 2 f 1 f sw p = type two compensation has only one gain level to be concerned with. this is the gain required to boost the control to output gain to 1 at the crossover frequency: (equation 26) cto fb g 1 g = to calculate the compensation component values (reference figure 8): first, select resistor r1. this topic is covered under ?determine the input resistor value? on page 15. resistor r3 may be selected at this time; however it is for setting the output dc level only, and is not used in the compensation calculations. r3 is covered under ?determine the output voltage setting resistor? on page 16. next, calculate the value of r2; r1 & r2 will set the gain for g fb : (equation 27) fb g 1 r 2 r = calculate the value for c1; c1 & r2 set the compensating zero frequency: (equation 28) 2 r ) 1 f ( 2 1 1 c z = finally, the value for c2 + c1 & r2 sets the compensating pole frequency: (equation 29) 1 ) 2 r 1 c ) 1 f ( 2 ( 1 c 2 c p ? ? ? =
LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 24 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 application information o utput mosfet s election when selecting output mosfets, there are five important parameters to be concerned with: maximum v ds rating, maximum drain current rating, rds on , total gate charge, and maximum power dissipation. the upper and lower mosfet positions, in many cases, can be satisfied with the same part value fet, making the use of dual mosfet packages attractive. however, in cases where output current and switching frequency are high, the mosfet chosen for the upper (control) fet may differ from the lower (synchronous) fet. for example, in a high frequen cy switcher application, the power dissipated in the control fet may be more dependent on switching losses, in which case a fet with a lower total gate charge (qg) should be considered. the opposite is true for the synchronous fet, where conduction losses may be the dominating factor in the total power dissipation. in this case a fet with a lower rds on would be considered. the maximum v ds rating of the mosfet should exceed by at least 10% the maximum dc input voltage, plus any voltage transients that might be present on the dc line, over all operating temperatures. the maximum drain current rating of the mosfet should be chosen to cover all operating current conditions, at all operating temperatures. over current limits, and current spikes should all be consider ed before selecting a mosfet. rds on and total gate charge should always be as small as possible. rds on and total gate charge (qg) will vary inversely with each other; ie. lower gate charges typically are at the expense of higher rds on ratings. mosfets must be chosen such that their maximum power dissipation is not exceeded at any time in the application, and that the junction temperature fo r the device does not exceed the maximum rating for the part under all conditions. the power dissipation of the mosfet will depend largely on two principle factors affecting lo ss: conduction losses, and switching losses. at lower frequency switching, conduction losses make up the bulk of the total power dissipation in the mosfets. two factors determine conduction losses: channel conduction losses (for both control and synchronous fets), and body diode conduction losses (synchronous fet only). for conduction losses in the control (upper) fet, channel loss is the only concern (under normal operation the body diode does not conduct). channel loss is due to the ir drop across the mosfet?s rds on . when calculating channel loss, rds on should be specified at the maximum junction temperature of the fet. most datasheets specify rds on at 25c, and provide a graph for estimating the rds on at a specific junction temperature. channel loss for the upper fet (pd rds(control) ) can be calculated with the following formula: (equation 30) ( ) in out n 0 2 load ) control ( rds v v rds i ) w ( pd = note: specify rds on at maximum junction temperature. for conduction losses in the synchronous (lower) fet, both channel and body diode losses must be considered. as in the control fet calculations, channel loss is a function of rds on , and should be evaluated using the specified rds on at the part?s specified maxi mum junction temperature: (equation 31) () ? ? ? ? ? ? ? ? ? = in out n 0 2 load ) sync ( rds v v 1 rds i ) w ( pd note: specify rds on at maximum junction temperature. in addition to channel loss, body diode conduction loss must be considered. body diode conduction loss (pd bd ) is found using the following equation: (equation 32) sw dt f load ) sync ( bd f t v i ) w ( pd = 2 where v f = body diode forward voltage t dt = pwm output dead time f sw = pwm output switching frequency switching losses for the synchronous fet are limited to the gate input losses due to the input capacitance (c iss ). pd ciss is found by: (equation 33) () sw gs iss ) sync ( ciss f v c . ) w ( pd = 2 5 0 where v gs = peak gate drive voltage most datasheets specify c iss in a graph of capacitance vs. v ds . due to the zero voltage switching of the synchronous fet, c iss should be chosen at v ds = 0 for this calculation.
LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 25 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 application information total power loss in the synchronous fet will be the sum of the conduction and the switching losses: (equation 34) ) sync ( ciss ) sync ( bd ) sync ( rds ) sync ( pd pd pd ) w ( pd + + = switching losses in the control fet are due to overlap switching loss, gate input loss, losses due to mosfet capacitances, and synchronous fet body diode reverse recovery charge. to calculate overlap switching loss, first the average gate current must be calculated. this is found through by the average of the upper and lower drive rds on , added to the mosfet internal gate resistance, which is specified on most datasheets. if not specified, 2.0 ohms may be substituted. in the LX1752, the average dr ive on-resistance is 3.0 ? . average gate current can now be found by: (equation 35) gate drive gs g r r v 5 . 0 i + = where r drive = average controller gate drive on resistance r gate = mosfet gate resistance once average gate current is known, the next step is to calculate the average gate switching time: (equation 36) g gd gs s i q q t + = 2 where q gs2 is the portion of gate to source gate charge after the gate reaches vth to the plateau of the gate charge curve, and q gd is mosfet gate-drain charge. refer to the mosfet datasheet for more detail. with switching time (t s ), load current, pwm frequency, and maximum v in known, overlap switching loss can be calculated by: (equation 37) sw in s out ols f v t i pd = gate input loss (pd gate ) is found by: (equation 38) gate drive gate sw gs g gate r r r f v q pd + = where: f sw = pwm switching frequency r gate = gate input resistance where q g = total gate charge (datasheet value) v gs = peak gate drive voltage r drive = high side driver on resistance losses due to synchronous fet reverse body diode recovery are based on q rr , a parameter not clearly defined in most datasheets. a good rule of thumb would be to increase the total power dissipation due to switching loss by 20% to account for losses due to q rr and mosfet capacitances. the total control fet switching loss would be the sum of the losses, increased by 20%: (equation 39) ( ) 2 1 . pd pd pd gate ols ) control ( sw + = total power dissipation in th e control fet can now be calculated: (equation 40) ) control ( rds ) control ( sw control pd pd ) w ( pd + = once the power dissipations of both mosfets are known, the operating junction temperatures can be calculated using thermal resistance specificati ons contained in the mosfet datasheet. p rinted c ircuit b oard l ayout r ecommendations careful attention to pcb layout is necessary to insure proper operation with minimal noise generation. when laying out the pcb, these guidelines should be followed: 1) keep the input capacitor, output capacitor, output inductor and output mosfets (upper and lower), close together, and tie all high current output returns directly to a suitable power ground plane. 2) keep the high curr ent ground return paths separate from the signal return paths. it is recommended that a separate signal ground plane be used, with a common tie point between the power ground plane and the signal ground plane established at the ic signal ground pin. 3) place the input dec oupling capacitor ha s close to the upper and lower mosfets as practical. connections between this capacitor an d the upper and lower mosfet?s drain and source co nnections should be as
LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 26 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 application information short as practical. 4) the ldo filter capacitor should be placed as close to the vccl pin as practical. 5) pgnd connection to the source pin of the lower mosfet should be as short as practical, and should be established with a direct connection (using no vias) if possible. 6) vs x pin connections should be kelvin connected directly at the upper mosfet?s drain pin(s). 7) hr x connection to the upper mosfet?s source pin should be as short as practical, and should be established with a direct connection (usi ng no vias) if possible. 8) lo x and ho x should be connected to their respective mosfet gate pins with as sh ort a trace as practical, and should be established with a direct connection (using no vias) if possible. 9) stray capacitance to ground on csx pins should be minimized. if possible, remove ground and power planes in the area directly below cs x pins, and place each respective cs x resistor as close to the LX1752 as practical; preferably on th e same pcb side as the LX1752. 10) place all compensation and feedback components as close to their respective error amplifier pins as practical. keep the error amplifier input connections (ea x -) as short as possible. 11) place the frequency programming resistor, r freq as close to the rfreq and gnd pins as practical. 12) refer to the evaluation board for an example of the pcb layout.
LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 27 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 package dimensions lq 28-pin 4x5mm d e e d2 e2 l k b a a1 a3 m illimeters i nches dim min max min max a 0.80 1.00 0.031 0.039 a1 0.00 0.02 0 0.008 a3 0.20 ref 0.008 ref k 0.20 ref 0.008 ref e 0.50 bsc 0.02 bsc l 0.30 0.50 0.012 0.02 b 0.18 0.30 0.007 0.012 d2 2.50 2.75 0.098 0.108 e2 3.50 3.75 0.138 0.148 d 4.00 bsc 0.158 bsc e 5.00 bsc 0.197 bsc
LX1752 p roduction d ata s heet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 28 www. microsemi . com dual interleaving pwm controller tm ? copyright ? 2007 rev. 1.0, 2008-07-31 l l x x 1 1 7 7 5 5 2 2 notes preliminary data ? information contained in this document is pre-production data and is proprietary to microsemi. it may not be modified in any way without the express written consent of microsemi. product referre d to herein is offered in pre-production form only and may not have completed microsemi?s quality assurance process for release to production. microsemi reserves the right to change or discontinue this proposed product at any time.

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